CSMC provide accurate and validated PDKs to our mutual customers for fast time-to-market by maximizing design productivity. These process packages consist of all the necessary components to design, simulate, layout, and verify a chip design, including schematic symbols, device Models, technology files, parameterized cells (pcells), physical verification decks(DRC/LVS/LPE), etc.
|Packaged design documents||PDH(process design handbook)||Process outline|
|Electrical Design Rule|
|Mask Tooling Table|
|ESD Protection Design GUIDELINE|
|Std.cell library&IO memory compiler|